jueves, 13 de mayo de 2010

LFSR contadores - 4 bits

Describo debajo un contador LFSR y su respectivo test bench.
El contador tiene un generic que es el valor de inicialización del LFSR cuando reset se activa. De este modo se pueden crear varias instances del contador LFSR con distintos valores iniciales de modo que cada contador tiene una cuente diferente en el mismo ciclo de reloj.

-- ------------------------------------------------------------------------ --
library ieee;

use ieee.std_logic_1164.all;

entity lfsr_4bits is
generic(initial_value: std_logic_vector(3 downto 0):= "1001");
port(
clk: in std_logic;
rst: in std_logic;
q_lfsr_4b: out std_logic_vector(3 downto 0)
);
end lfsr_4bits;

architecture beh of lfsr_4bits is

signal q_lfsr_4b_i: std_logic_vector(3 downto 0);

begin

lfsr_cnt_proc: process(rst, clk)
begin
if(rst= '1' ) then
q_lfsr_4b_i <= initial_value;
elsif (rising_edge(clk)) then
q_lfsr_4b_i <= q_lfsr_4b_i(2 downto 0) &
(q_lfsr_4b_i(3) xor q_lfsr_4b_i(2));
end if;
end process lfsr_cnt_proc;

q_lfsr_4b <= q_lfsr_4b_i;

end architecture beh;
-- ------------------------------------------------------------------- --
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity lfsr_4bits_tb is
end lfsr_4bits_tb;

architecture test of lfsr_4bits_tb is

component lfsr_4bits is
generic(initial_value: std_logic_vector(3 downto 0));
port(
clk: in std_logic;
rst: in std_logic;
q_lfsr_4b: out std_logic_vector(3 downto 0)
);
end component;

signal clk: std_logic:='0';
signal rst: std_logic;
signal q_lfsr_4b: std_logic_vector(3 downto 0);

begin


clk <= not clk after 50 ns;
rst <= '1', '0' after 250 ns;

u1: lfsr_4bits
generic map ("1011")
port map(
clk => clk,
rst => rst,
q_lfsr_4b => q_lfsr_4b
);

end architecture test;

-- ----------------------------------------------------------------------- --

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